Optically-controlled Phase Change Memories
Phase change memory (PCM) is a class of non-volatile memory (NVM) that is a promising alternative to DRAM, which is experiencing increased leakage power consumption with technology scaling. The stored data is encoded in the phase state of the memory cell. Recent advances in device research have demonstrated PCM cells that are optically-controlled. The optical signals in high-bandwidth low-latency silicon-photonic interconnects provide high read and write throughput. My project aims at architecting a PCM memory that is optically-controlled with customized read and write protocols that can replace DRAM as a high-throughput main memory. Such a non-volatile memory system would open interesting opportunities for designing efficient memory architectures, in-memory computing systems and accelerator-specific memory designs.
Photonic Network-on-chips for 2.5D Manycore Systems (TCAD'20, DATE'20, DATE'19)
Growing performance demands and prominence of abundant-data applications are driving design of many-core systems and larger bandwidth demands from on-chip interconnects that connect the cores and memories. With the emergence of silicon photonic technology, photonic network-on-chips (PNoCs) have been shown to demonstrate low latency, high bandwidth density, low energy-per-bit communication at negligible data-dependent power. However, the power overhead of lasers, thermal tuning, and electrical-optical conversion present major challenges against the wide-scale adoption of silicon photonic technology. My project aims at developing cross-layer modeling methodologies and optimizations that seek to bridge the gap between device/circuit level and system/application level towards designing an energy-efficient PNoC.
Page Allocation in Heterogeneous Memory Systems (IPDPS'18, BARC'18)
The recent digital data explosion in the field of machine learning, artificial intelligence, cloud computing and big data applications demands the need for continuous and massive amounts of data transfers between the computing elements and the memory hierarchies. The continued growth in raw performance of data center computing is driving increased bandwidth demands on the main memory. Heterogeneous memory systems, consisting of different memory modules, have been demonstrated to overcome these power-performance tradeoffs in data center computing. My work focuses on developing a heterogeneity-aware page allocation policy based on the page’s access behaviors for heterogeneous memory systems. I developed a framework (MOCA) to characterize a memory page at a fine granularity of memory objects. At runtime, I designed an allocation algorithm to allocate this page to the best-suited memory module in the target heterogeneous memory system.
ABCStar front-end chip for the ATLAS Silicon Strip Upgrade (TWEPP'16)
The next step for the Large Hardron Collider (LHC) will be a High Luminosity upgrade, referred to as the HL-LHC project. An improved radiation resistant and more granular detector structure will be required for the tenfold higher instantaneous luminosity, and the much higher track density, after the Phase 2 upgrade. The principal objective of the ATLAS experiment is to replace the current Inner Detector with a new tracking system, named the ITk. To meet the higher ATLAS upgrade trigger requirement, a fast readout architecture with lower latencies and increased bandwidth is imminent. The ATLAS Binary Controller (ABC130) and Hybrid Controller Chip (HCC) were designed and fabricated at the IBM130nm technology.